\contentsline {chapter}{List of Figures}{viii}
\contentsline {chapter}{List of Tables}{xi}
\contentsline {chapter}{Acknowledgments}{xii}
\contentsline {chapter}{\numberline {1}Introduction to Statistical High-Level Synthesis}{1}
\contentsline {section}{\numberline {1.1}The Influence of Process Variations on HLS}{3}
\contentsline {section}{\numberline {1.2}Key Issues in Statistical High-level Synthesis}{8}
\contentsline {subsection}{\numberline {1.2.1}Library Characterization and Statistical Analysis}{8}
\contentsline {subsection}{\numberline {1.2.2}Statistical Timing and Power Analysis for HLS}{9}
\contentsline {subsection}{\numberline {1.2.3}Existing Work on Variation-aware High-level\\ Synthesis}{10}
\contentsline {section}{\numberline {1.3}High-Level Synthesis for Three Dimensional Integrated Circuits}{12}
\contentsline {section}{\numberline {1.4}Contributions and Organization}{13}
\contentsline {chapter}{\numberline {2}ILP-based Scheme for Timing Variation-aware Scheduling and Resource Binding}{16}
\contentsline {section}{\numberline {2.1}Introduction}{17}
\contentsline {section}{\numberline {2.2}Related Work}{18}
\contentsline {section}{\numberline {2.3}Timing Variation-Aware High-Level\\ Synthesis}{19}
\contentsline {subsection}{\numberline {2.3.1}Yield Aware Resource Partitioning}{20}
\contentsline {subsection}{\numberline {2.3.2}Calculation of Overall Timing Yield}{21}
\contentsline {section}{\numberline {2.4}ILP Formulation with Timing Yield\\ Constraint}{23}
\contentsline {subsection}{\numberline {2.4.1}Problem Definition}{23}
\contentsline {subsection}{\numberline {2.4.2}ILP Formulation}{24}
\contentsline {subsubsection}{\numberline {2.4.2.1}Basic ILP Framework}{24}
\contentsline {subsubsection}{\numberline {2.4.2.2}Timing Yield Constraints and Objective Functions}{25}
\contentsline {section}{\numberline {2.5}Experimental Results}{26}
\contentsline {section}{\numberline {2.6}Summary}{29}
\contentsline {chapter}{\numberline {3}Tolerating Process Variations in High-Level Synthesis Using Transparent Latches}{31}
\contentsline {section}{\numberline {3.1}Introduction}{32}
\contentsline {section}{\numberline {3.2}Related Work}{33}
\contentsline {section}{\numberline {3.3}Preliminaries and Motivating Example}{34}
\contentsline {subsection}{\numberline {3.3.1}Timing Yield in High-Level Synthesis}{34}
\contentsline {subsection}{\numberline {3.3.2}Motivation of Replacing Flip-flops with Latches}{37}
\contentsline {section}{\numberline {3.4}Converting Traditional Design to \\Latch-based Design}{39}
\contentsline {subsection}{\numberline {3.4.1}Potential Violations in Latch-based Design}{39}
\contentsline {subsection}{\numberline {3.4.2}Latch Replacement with Lifetime Extension}{41}
\contentsline {section}{\numberline {3.5}Latch Replacement Framework}{42}
\contentsline {subsection}{\numberline {3.5.1}Data Preparation}{42}
\contentsline {subsection}{\numberline {3.5.2}Replacement Algorithm}{43}
\contentsline {subsection}{\numberline {3.5.3}Evaluation of Timing Yield Improvement}{44}
\contentsline {subsection}{\numberline {3.5.4}Overhead Estimation}{45}
\contentsline {section}{\numberline {3.6}Experimental Results}{47}
\contentsline {section}{\numberline {3.7}Summary}{49}
\contentsline {chapter}{\numberline {4}Parametric Yield Driven Resource Binding in Behavioral\\ Synthesis with Multi-$V_{th}/V_{dd}$ Library}{51}
\contentsline {section}{\numberline {4.1}Introduction}{52}
\contentsline {section}{\numberline {4.2}Related Work}{54}
\contentsline {section}{\numberline {4.3}Multi-$V_{th}$/$V_{dd}$ Library Characterization \\Under Process Variations}{55}
\contentsline {subsection}{\numberline {4.3.1}Variation-aware Library Characterization Flow}{55}
\contentsline {subsection}{\numberline {4.3.2}Multi-$V_{th}/V_{dd}$ Library Characterization}{57}
\contentsline {section}{\numberline {4.4}Yield Analysis in Statistical High-Level Synthesis}{58}
\contentsline {subsection}{\numberline {4.4.1}Parametric Yield}{58}
\contentsline {subsection}{\numberline {4.4.2}Statistical Timing and Power Analysis for HLS}{60}
\contentsline {subsection}{\numberline {4.4.3}Voltage Level Conversion in HLS}{61}
\contentsline {section}{\numberline {4.5}Yield-Driven Power Optimization Algorithm}{62}
\contentsline {subsection}{\numberline {4.5.1}Overview of the Variation-aware Resource Binding Algorithm}{63}
\contentsline {subsection}{\numberline {4.5.2}Voltage Level Conversion Strategies}{63}
\contentsline {subsection}{\numberline {4.5.3}Moves Used in the Iterative Search}{65}
\contentsline {subsection}{\numberline {4.5.4}Algorithm Analysis}{66}
\contentsline {section}{\numberline {4.6}Experimental Results}{67}
\contentsline {section}{\numberline {4.7}Summary}{71}
\contentsline {chapter}{\numberline {5}Minimizing Leakage Power in Aging-Bounded High-level \\Synthesis}{73}
\contentsline {section}{\numberline {5.1}Introduction}{74}
\contentsline {section}{\numberline {5.2}NBTI and Leakage Characterization}{77}
\contentsline {subsection}{\numberline {5.2.1}NBTI Modeling}{77}
\contentsline {subsection}{\numberline {5.2.2}NBTI and Leakage Characterization for Multi-$V_{th}$ Library Components}{79}
\contentsline {subsection}{\numberline {5.2.3}Motivation Example}{81}
\contentsline {section}{\numberline {5.3}Leakage Optimization in Aging-bounded \\High-Level Synthesis}{84}
\contentsline {subsection}{\numberline {5.3.1}Aging-bounded HLS}{84}
\contentsline {subsection}{\numberline {5.3.2}Leakage Optimization in Aging-bounded HLS}{85}
\contentsline {section}{\numberline {5.4}Experiments and Result Analysis}{89}
\contentsline {section}{\numberline {5.5}Summary}{94}
\contentsline {chapter}{\numberline {6}Incorporating High-Level Synthesis in Physical Planning of\\ Three Dimensional (3D) ICs}{95}
\contentsline {section}{\numberline {6.1}Introduction}{96}
\contentsline {section}{\numberline {6.2}Related Work}{97}
\contentsline {section}{\numberline {6.3}The Problem Definition}{98}
\contentsline {subsection}{\numberline {6.3.1}Design Space Exploration in High-Level Synthesis}{99}
\contentsline {subsection}{\numberline {6.3.2}3D Physical Planning}{99}
\contentsline {subsection}{\numberline {6.3.3}Problem Formulation}{100}
\contentsline {section}{\numberline {6.4}Experiment Analysis and Case Studies}{104}
\contentsline {subsection}{\numberline {6.4.1}Results for Design Space Exploration in High-Level Synthesis}{105}
\contentsline {subsection}{\numberline {6.4.2}Results of the Incorporated 3D Physical Planning Flow}{106}
\contentsline {section}{\numberline {6.5}Summary}{107}
\contentsline {chapter}{\numberline {7}System-level Design Space Exploration for Three-Dimensional (3D) SoCs}{108}
\contentsline {section}{\numberline {7.1}Introduction}{109}
\contentsline {section}{\numberline {7.2}Related Work}{110}
\contentsline {section}{\numberline {7.3}Preliminaries and Motivational Example}{111}
\contentsline {subsection}{\numberline {7.3.1}Preliminaries on 3D IC Stacking}{111}
\contentsline {subsection}{\numberline {7.3.2}Preliminaries on Architectural Co-design}{112}
\contentsline {subsection}{\numberline {7.3.3}An Motivational Example}{113}
\contentsline {section}{\numberline {7.4}System-Level Synthesis Framework for 3D ICs}{114}
\contentsline {subsection}{\numberline {7.4.1}Architecture Synthesis Framework}{114}
\contentsline {subsection}{\numberline {7.4.2}Resource Allocation}{115}
\contentsline {subsection}{\numberline {7.4.3}Layer Assignment}{118}
\contentsline {subsection}{\numberline {7.4.4}Task Scheduling}{120}
\contentsline {subsection}{\numberline {7.4.5}Cost Function}{120}
\contentsline {section}{\numberline {7.5}Analysis and Case Study of 3D ESL\\ Exploration}{122}
\contentsline {section}{\numberline {7.6}Summary}{124}
\contentsline {chapter}{\numberline {8}Conclusion and Future Work}{125}
\contentsline {chapter}{Bibliography}{128}
